The present invention relates generally to output drivers, and in particular to output drivers that must meet specified output impedance and current characteristics.
Output drivers are well known in the electronic arts. An output driver typically comprises a xe2x80x9cpull-upxe2x80x9d transistor that is on when the output signal needs to transition from a low to high value and a xe2x80x9cpull-downxe2x80x9d transistor that is on when the output signal needs to transition from high to low.
FIG. 1 illustrates a typical CMOS output driver 10. Pad 12 is the point of signal output. The term xe2x80x9cpadxe2x80x9d as used herein simply means the point of signal output and does not have any other more limited meaning. Typically, in an application involving a system bus, e.g. a Universal Serial Bus, the output will be to a cable such as cable 13. A typical cable will present a capacitive load to a signal output at pad 12. Such a load is represented by capacitor 14 which has a capacitance C1. When the signal voltage value at input 11 is high, the voltage value at gate G1-1 of pull-up transistor Ni-i is high, and, due to inverter 15, the voltage value at gate G2-1 of pull-down transistor N2-1 is low. As a result, transistor N1-1 is on, transistor N2-1 is off, and pull-up current ILH flows as shown, charging up capacitive load 14 and driving the voltage at pad 12 to a high value. Conversely, when the signal voltage value at input 11 is low, transistor N1-1 is off and pull-down transistor N2-1 is on. As a result, pull-down current IHL flows draining the charge on the cable and bringing the voltage at pad 12 down to a low level.
In some applications, it is desirable for output drivers to meet particular output impedance and signal transition time characteristics. For example, Revision 1 of the Universal Serial Bus Specification sets forth particular driver requirements. In particular, the output impedance must be between 3 ohms and 15 ohms. Furthermore, the signal transition times (rise time and fall time) must be between 4-20 ns and the high signal voltage must be between 2.8 v-3.6 v. Assuming constant capacitance, and because I=Cdv/dt, the signal transition time and signal voltage requirements effectively set a current requirement. For example, assuming a high voltage of 3.2 v and a transition time of 12 ns (both values in the middle of the USB required range) and assuming C=50 pF, ILH=IHL=50 PF(3.2 v/12 ns)=13.3 mA. However, given the characteristic voltage/current relationship of a CMOS transistor, delivering a desired output current during signal transitions can be difficult.
FIG. 2 shows an example of the possible approximate shapes of the voltage/current curves for a typical NMOS transistor, such as pull-down transistor N2-1 in the output driver 10 of FIG. 1. These curves help illustrate the difficulty of meeting particular output current and impedance requirements. Pull-down transistor N2-1 has three terminals: drain D2-1, source S2-1, and gate G2-1. FIG. 2 shows 3 curves. Each curve illustrates the relationship between the drain-to-source voltage VDS and the drain-to-source current IDS for a given gate-to-source voltage VGS.
In a typical driver circuit, the gate-to-source voltage VGS would be substantially constant at, for example, VGS1. In output driver 10, the pad output voltage at pad 12 is the same as the drain-to-source voltage VDS of the pull-down transistor N2-1. If the ideal output current is IHL=IDS=IDS1, then VGS will typically be set at VGS=VGS1. As illustrated along the VGS1 curve in FIG. 2, the impedance Z=V/I is steadily decreasing as VDS drops toward VDS1. However, once VDS drops below VDS1, the impedance is not decreasing rapidly enough to maintain the current level, and IDS begins to drop below IDS1. For example, when VDS has dropped to VDS2, IDS=IDS2.
For some applications, such as an output driver for use under the USB specification requirement, the output impedance of a driver such as driver 10 will be too high in the regions of low drain-to-source voltage. Thus IDS will drop too low during the signal transition and the signal transition time may be too slow. If the gate-to-source voltage were set at a higher value, such as VGS2, the impedance when VDS=VDS2 would be relatively lower and a higher transition current IDS=IDS1 would be maintained even as the output voltage VDS dropped. However, in a driver such as driver 10 in FIG. 1, VGS cannot be set at VGS2 during the entire transition because when VDS is greater than VDS2, the output transition current will be too high, and USB or other specification requirements might not be met.
FIG. 3 illustrates an earlier driver 30 known in the art for attempting to deal with the problem of maintaining steady current flow during signal transitions. During the low to high transition, pull-up transistors P1-3 and P2-3 turn on at different times. When an input signal first transitions from low to high, P1-3 turns on and pull-up current ILH1 begins to flow, driving up the voltage at pad 32 (pad 32 is attached to cable 33 which is a capacitive load as represented by capacitor 34 having a capacitance C2). As the output voltage at pad 32 increases, the source-to-drain voltage of transistor P1-3 decreases, and eventually pull-up current ILH1 begins to decrease. However, after a delay due to delay circuit D1-3, transistor P2-3 turns on and pull-up current ILH2 begins to flow, and the overall output pull-up current becomes ILH1+ILH2. Conversely, during the high to low transition, pull-down transistors N1-3 and N2-3 are turned on at different times. When an input signal at input 31 first transitions from high to low, pull-down transistor N1-3 turns on and pull-down current IHL1 begins to flow. However, as the voltage at pad 32 decreases, the drain-to-source voltage of transistor N1-3 also begins to drop and eventually, pull-down current IHL1 begins to decrease. After a delay caused by delay circuit D2-3, pull-down transistor N2-3 is turned on and output current IHL2 begins to flow. Thus the overall pull-down current becomes IHL1+IHL2.
This staggering of two pull-up and two pull-down transistors should, in theory, allow relatively steady pull-up and pull-down currents to be maintained during signal transitions. However, implementing delay circuits that deliver the proper amount of delay to obtain desirable results is difficult. Variations in operating parameters cause variations in the delay implemented by delay circuits D1-3 and D2-3. If the delay is too short, then the output impedance is too low at the beginning of a signal transition and the output current will be too high. If the delay is too long, the output impedance will remain too high as the as the signal transition progresses, and the transition output current will be too low, or possibly even drop to zero.
A present embodiment of the invention provides one or more voltage response circuits that modify a voltage difference between a first terminal and a second terminal of a pull-up or pull-down transistor in response to a change in a voltage difference between a third terminal and the second terminal of the pull-up or pull-down transistor. As a result, the transistor""s impedance and current flow may be adjusted to better meet the requirements of particular applications.